We are looking for fresh graduates now. We have various career opportunities available in Design and Development Engineering.
The fresh graduates will be involving in the training, design and development of next generation SOC for wide range of Intel products (ranging from Client PC, smartphone, tablet to wearable). Responsibilities will include but not limited to:
- Assist design unit owner in Register Transfer Level (RTL) model functional validation. Use CAD tool extensively to simulate logic behavior and circuit performance and direction of physical design for next generation, deep sub-micron embedded circuit solutions. Verify the circuit behavior against the original simulation model and first silicon.
- Define VLSI Structural Design methodology and developing design flows. Implement structural physical designs, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration. Verify structural physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power.
- Develop Analog IP on next generation deep submicron process for the Intel’s SOC, perform tasks related to Very-large-scale integration (VLSI) complementary metal-oxide-semiconductor (CMOS) IC design, Solid state physics and physical layout. Such tasks may include: Circuit design of high speed clocking related circuits [phase-locked loop (PLL), delay-locked loop (DLL), bandgap] or high voltage input/output (IO) [double data rate (DDR)/LPDDR, General-purpose input/output (GPIO), OPIO].
- Responsible for Integration of Third party IPs — Synthesis, functional and/or timing convergence, and pre and post-si debug of IPs developed by various external vendors as well as within the company. Handling of signals crossing power planes and clock domains, industry standard protocols including hardware and software details dealing with Memory (LPDDR), storage (eMMC, SATA, UFS), peripherals (PCIe, USB), and MIPI interfaces in SOC devices. System integration dealing with Si/ Platform/ FW/ MW/ drivers/ OS/ Apps on Android & Windows-based tablets and phones.
- Fresh graduates or graduated < 18 months are eligible.
- CGPA requirement is CGPA 3.0 BUT students with good exposure on FYP or good result on Core Engineering subjects are strongly encouraged to apply
- Student currently pursuing studies in relevant field with good understanding of semiconductor physics, basic PC computer architecture or computer science.
- Additional advantages: Familiarity with Very Large Scale Integration (VLSI) Complementary Metal-Oxide Semiconductor (CMOS) logic circuit design – Well versed in UNIX*, C programming and relevant Computer Aided Design (CAD) tools
- Basic pay : RM3150 (Bachelor), RM4200 (Master); RM6000 (PhD)
- Hiring bonus : 0.5 months
- Conversion bonus : 2 months for those being converted to permanent employee
- Annual leave : 14 days per year
NOTE: These are not the full list of benefits.
Interested candidates, kindly email CV to Dr Teh Eong Yap